Not applicable.
Not applicable.
1. Field of the Invention
The present invention relates generally to a system for supporting peripheral components that couple to a high speed peripheral bus, such as a PCI bus. More particularly, the present invention relates to a system which checks the capability of peripheral components to operate at particular clock frequencies of the peripheral bus. Still more particularly, the present invention relates to a system which includes a plurality of expansion slots coupled to a variable speed peripheral bus, and that determines which clock frequency to use for the bus based upon the characteristics of the devices that populate the expansion slots.
2. Description of the Prior Art
FIG. 1 is a block diagram that illustrates a prior art computer system 10 including a microprocessor (CPU) 12, a system memory 14, and a bus bridge 16. A local bus 18 couples the microprocessor 12 to the bus bridge 16. A memory bus 20 couples system memory 14 to bus bridge 16. A first peripheral device 22 and a second peripheral device 24 are coupled to the bus bridge 16 through a peripheral bus 25.
The peripheral bus 25 may comprise a high performance PCI bus capable of supporting a plurality of PCI master and slave devices. Thus, the peripheral device 22 may comprise PCI Master controller that is capable of asserting ownership of the PCI bus during PCI Master cycles. The PCI master device 22 may comprise a local area network (LAN) device that connects other computer systems to peripheral bus 25, or could be embodied by an expansion bus interface that connects peripheral bus 25 to other peripheral buses. A second peripheral device 24 also is shown coupled to the peripheral bus 25. Peripheral device 24 may comprise a PCI slave device, such as a disk controller device or an audio controller device, for example. In accordance with normal convention, the PCI peripheral devices may be coupled via expansion slots to the PCI bus, thus permitting the user to configure the computer system 10 by adding peripheral devices to the system that are capable of coupling to the PCI bus.
The microprocessor 12 shown in FIG. 1 may comprise one or more of any of the various Intel Pentium-class microprocessors, and the local bus 18 could comprise a Pentium style local bus. Other style microprocessors and/or local bus architectures may be used without departing from the principles of the present invention. Details regarding the various bus cycles and protocols of the Pentium local bus 18 are not discussed in detail herein, as they are well known by those in the art, and are available in numerous publications.
The bus bridge 16 provides a standard interface between the CPU local bus 18 and the PCI bus 25. As such, the bus bridge 16 orchestrates the transfer of data, address, and control signals between two buses. PCI bus 25 typically comprises a high performance peripheral bus that includes multiplexed data/address lines, and which supports burst-mode transfers. Additional features regarding the PCI bus are described in the publication xe2x80x9cPCI Local Bus Specification,xe2x80x9d Revision 2.2, Dec. 18, 1998, PCI Special Interest Group, Hillsboro, Oreg. the details of which are incorporated by reference herein.
As set forth in Revision 2.2 of the xe2x80x9cPCI Local Bus Specification,xe2x80x9d the PCI bus comprises a synchronous bus with a generally uniform clock. The PCI bus clock signal typically is generated by circuitry in the bus bridge 16 and transmitted via the PCI CLK line to each of the devices resident on the PCI bus 25. Although shown in FIG. 1 as a separate signal line, as one skilled in the art will understand the PCI CLK line may comprise one of the signal lines in the PCI bus 25.
Relatively recent modifications to the PCI Bus Specifications have been made to permit operation of the bus at higher clock speeds. See generally Chapter 7 of the PCI Local Bus Specification, Revision 2.2. One problem with implementing a high speed PCI bus is that some PCI peripheral devices, particularly those devices developed in the past, simply are not capable of operating at the higher clock speeds. For many years the PCI bus was only capable of 33 MHz operation. Consequently, peripheral devices intended for coupling to a PCI bus were designed during this period to operate at 33 MHz. Because of this limitation, such peripheral devices may be incapable of operation at higher speed environments, such as at the 66 MHz clock speed available today. Use of these slower speed peripheral devices may cause the entire bus to malfunction if the PCI bus is operated at 66 MHz.
To address this problem, a 66 MHz ENABLE control line is included as part of the PCI bus 25, as shown in FIG. 1. The 66 MHz ENABLE line couples to a voltage source Vcc, and to each PCI slot provided in the system. If a peripheral device inserted in a PCI slot is incapable of 66 MHz operation, the 66 MHz ENABLE pin on the peripheral device connects to ground to pull the 66 MHz ENABLE line low. This, in turn, is detected by the bus bridge 16, which responds by slowing the operating speed of the bus to 33 MHz. In this manner, the bus bridge only drives a 66 MHz clock if all peripheral devices support 66 MHz operation.
While the use of the 66 MHz ENABLE line addresses some of the concerns regarding incompatible clock speeds, there still remain some problems that result from the use of a peripheral bus capable of operating at multiple speeds. One problem is that the bus bridge may be unable to drive the faster data and control signals to multiple expansion slots. As noted in Chapter 7 of the xe2x80x9cPCI Local Bus Specification,xe2x80x9d Revision 2.2, the xe2x80x9c66 MHz PCI requires faster timing parameters and redefined measurement conditions. As a result, 66 MHz PCI buses may support smaller loading and trace lengths.xe2x80x9d Thus, the 66 MHz clocking of the PCI bus mandates fewer peripheral devices and shorter leads to the peripheral devices. Consequently, computer systems that support dual 33 MHz/66 MHz operation on the same PCI bus must typically limit the number of available PCI slots to prevent too many 66 MHz devices from being connected to the PCI bus, Because of the loading and trace limitations of the 66 MHz bus, some manufacturers of bus bridges and associated chipsets recommend that a computer system only include two PCI slots to prevent more than two 66 MHz peripheral devices from being coupled to the PCI bus bridge. This approach to handling the problem of loading at higher clock frequencies can be Draconian. A user who desires to run more than two peripheral devices at the slower clock frequency (i.e. 33 MHz) cannot do so, even though the system would support these devices, because not enough expansion slots are provided. Thus, limiting the number of expansion slots to overcome limitations in driving peripheral devices at higher frequencies penalizes the user desiring more expansion slots at slower clock frequencies.
It would be advantageous if a system were developed which could include more slots than could be driven at the higher clock frequency, and which would reduce the frequency of the bus clock if an excessive number of peripheral components were installed in the expansion slots. Preferably, the system would detect the capabilities of the installed peripheral components and adjust the clock frequency of the bus to the highest possible setting based upon those capabilities, and the capability of the bus bridge to drive the data and control signal to the populated expansion slots. Despite these and other readily apparent advantages of such a system, to date no such system has been developed.
The present invention solves the shortcomings and deficiencies of the prior art by providing a computer system that automatically determines whether a peripheral device is present in each expansion slot, and whether each device is capable of high clock frequency (such as, for example, 66 MHz) operation. If any PCI device cannot operate at the high clock frequency or if the bus bridge is incapable of driving the number of devices present at the higher clock frequency, the system automatically drives the PCI bus clock signal at a standard, lower frequency (such as, for example, 33 MHz). Conversely, if the PCI devices present are operable at the higher frequency and the bus bridge can drive the higher speed bus to the number of installed peripheral devices, the system operates the PCI bus clock signal at the higher frequency (66 MHz, for example).
The present invention includes a bus bridge which orchestrates the transfer of address and data signals between the PCI bus and a local bus. The bus bridge preferably includes a clock driver, which generates the PCI bus clock signal, at a frequency dependent on the status of a high frequency enable (66 MHz ENABLE in the preferred embodiment) line. An expansion slot controller couples to each PCI expansion slot and to the 66 MHz ENABLE line. The 66 MHz ENABLE line is asserted high by the expansion slot controller if the system supports operation at 66 MHz. The expansion slot controller determines if a peripheral device is present in an expansion slot, and also determines if the device is capable of supporting operation at the higher clock frequency. After determining the status of each expansion slot, the expansion slot controller determines if all of the peripheral devices can support high frequency operation, and also determines if the bus bridge can drive the number of devices present. Based upon this determination, the expansion slot controller can drive the 66 MHz ENABLE line low to indicate that the PCI bus must be operated at a lower frequency, or can drive the 66 MHz ENABLE line high. If the 66 MHz ENABLE line is deasserted by the expansion slot controller, the bus bridge drives the PCI bus signals at a standard clock frequency, such as 33 MHz. Conversely, if the expansion slot controller does not drive the 66 MHz ENABLE line low, then the bus bridge drives the PCI bus signals at the higher frequency, such as 66 MHz.